1. Field
Exemplary embodiments of the present invention relate to a majority determination circuit, a majority determination method, and a semiconductor device for reducing error when determining a majority.
2. Description of the Related Art
Data processing speed influences the performance of a semiconductor integrated circuit, for example, a main memory or a graphic memory for storing data in response to the control of a central processing unit (CPU) or a graphic processing unit (GPU).
Data bus inversion (DBI) is a technique for increasing data processing speed. According to DBI, for example, data is inverted and transmitted if four or more bits of eight bits of data are at a high level or a low level whereas data is transmitted without inversion if it is not. Thus, DM minimizes the number of switching times of output data and increases data processing speed.
In order to perform the DBI, a majority determination circuit is required for comparing the number of high-level bits with the number of low-level bits in data transmitted through a data bus and determining which level of bits is a majority.
FIG. 1 is a circuit diagram illustrating a conventional majority determination circuit.
As shown in FIG. 1, the majority determination circuit includes a plurality of first NMOS transistors N0 to N7 configured to be turned on/off in response to each bit D<0> to D<7> of data D<0:7> a plurality of second NMOS transistors N8 to N15 configured to be turned on/off in response to each bit DB<0> to DB<7> of inverted data DB<0:7> obtained by inverting data D<0:7>, PMOS transistors P0 and P1, dummy transistors DN0 and DN1 and a current source IS.
The majority determination circuit will be described with reference to FIG. 1.
Each of the plurality of first NMOS transistors N0 to N7 is coupled to a first node NO1, wherein each of the first NMOS transistors N0 to N7 is turned on to sink current flowing through the first node NO1 when a bit corresponding to itself is at a high level, and is turned off when the corresponding bit is at a low level. Each of the plurality of second NMOS transistors N8 to N15 is coupled to a second node NO2, wherein each of the second NMOS transistors is turned on to sink current from the second node NO2 when a bit corresponding to itself is at a high level, and is turned off when the corresponding bit is at a low level.
The first PMOS transistor P0 is connected between a power supply voltage VDD and the first node NO1 and sources current flowing through the first node NO1 in response to the voltage of the first node NO1. The second PMOS transistor is connected between the power supply voltage VDD and the second node NO2 and sources current flowing through the second node NO2 in response to the voltage of the first node NO1.
The first dummy transistor DN0 is coupled to the first node NO1 and has a gate to which a base voltage VSS is applied, thereby being in a turned-off state. The second dummy transistor DN1 is coupled to the second node NO2, and has a gate to which a power supply voltage VDD is applied, thereby being in a turned-on state. The second dummy transistor DN1 sinks current flowing through the second node NO2. Current sunk by each NMS transistor of the plurality of transistors N0 to N15 is equal to each other and the amount of current sunk by one dummy transistor is less than the amount of current sunk by the plurality of transistors N0 to N15.
A voltage of the second node NO2 corresponds to a majority determination result of the majority determination circuit. When, among the respective bits of data D<0:7>, the number of high-level bits is greater than the number of low-level bits, the number of turned-on transistors among the plurality of first transistors N0 to N7 is greater than the number of turned-on transistors among the plurality of second transistors N8 to N15. Accordingly, the amount of current sunk from the first node NO1 is greater than the amount of current sunk from the second node NO2, and thus a voltage corresponding to a high level is outputted to the second node NO2. When, among the respective bits of data D<0:7>, the number of low-level bits is greater than the number of high-level bits, the number of turned-on transistors among the plurality of second transistors N8 to N15 is greater than the number of turned-on transistors among the plurality of first transistors N0 to N7. Accordingly, the amount of current sunk from the first node NO1 is less than the amount of current sunk from the second node NO2, and thus a voltage corresponding to a low level is outputted to the second node NO2.
When, among the respective bits of data D<0:7> the number of high-level bits is equal to the number of low-level bits, the amount of current sunk by the plurality of first transistors N0 to N7 is equal to the amount of current sunk by the plurality of second transistors N8 to N15, but the amount of current sunk from the second node NO2 is relatively greater due to the dummy transistors DN0 and DN1, so that a voltage corresponding to a low level is outputted to the second node NO2. That is to say, a weight is given by dummy transistors, so that it is possible to output a specific logic value to the second node NO2 even when, among the respective bits of data D<0:7>, the number of high-level bits is equal to the number of low-level bits.
However, although a weight is applied using a dummy transistor, a distortion of data due to noise or the like, or a concern in impedance matching with an external device may cause error in data determination.